QLC drives have fewer write-cycles than TLC and if their data is not refreshed periodically (which their controllers will automatically do when powered) the data in them gets corrupted faster.
In other words, under heavy write usage they will last less time and at the other end when used for long term storage of data, they need to be powered much more frequently merelly to refresh the stored states (by reading and writting back the data).
So moving to QLC in cloud application comes with mid and long terms costs in terms of power usage and, more importantly, drive end-of-life and replacement.
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Quad Level Cell SSD technology stores 4 bits per cell - hence 16 levels - whilst TLC (Triple Level Cell) stores 3 bits - hence 8 levels - so the voltage difference between levels is half as much, and so is the margin between levels.
Everything deep down is analog, so the digital circuitry actually stores analog values on the cells at then reads them back and converts them to digital. When reading that analog value, the digital circuit has to decide to which digital value that analog value actual maps to, which it does by basically accepting any analog value within a certain range aroun the mathematically perfect value for that digital state.
(A simple example: in a 3.3V data line, when the I/O pin of a microcontroller reads the voltage it will decide for example that anything below 1.2V is a digital LOW (i.e. a zero), anything above 2.1V is a HIGH (a one) and anything in between is an erroneous value - i.e. no signal or a corrupted signal - this by the way is why if you make the line between a sender and a receiver digital chip too long, many meters, or change the signals in them too fast, hundreds of MHz+, without any special techniques to preserve signal integrity, the receiver will mainly read garbage)
So the more digital levels in a single cell the narrower the margin, the more likely that due to the natural decay over time of the stored signal or due cell damage from repeat writes, the analog value the digital circuitry reads from it be too far away from the stored digital level and be at best marked as erroneous or at worse be at a different level and thus yield a different digital value.
All this to say that QLC has less endurance (i.e. after fewer writes the damage to the cells from use causes that what is read is not the same value as what was written) and it also has less retention (i.e. if the cell is not powered, the signal decay will more quickly cause stored values to end up at a different level than when written).
Now, whilst for powered systems the retention problem is not much of an issue for cloud storage (when powered, the system automatically goes through each cell, reading its value and writting it back to refresh what’s stored there back to the mathematically perfect analog value) with just a slightly higher consumption over time for data that’s mainly read only (for flash memory, writting uses way more power than reading), the endurance problem is much worse for QLC because the cells will age twice as fast over TLC for data that is frequently written (wear-leveling exists to spreads this effect over all cells thus giving higher overall endurance, but wear-leveling is also in there for TLC so it does not improve the endurance of QLC).
TL;DR
QLC drives have fewer write-cycles than TLC and if their data is not refreshed periodically (which their controllers will automatically do when powered) the data in them gets corrupted faster.
In other words, under heavy write usage they will last less time and at the other end when used for long term storage of data, they need to be powered much more frequently merelly to refresh the stored states (by reading and writting back the data).
So moving to QLC in cloud application comes with mid and long terms costs in terms of power usage and, more importantly, drive end-of-life and replacement.
–
Quad Level Cell SSD technology stores 4 bits per cell - hence 16 levels - whilst TLC (Triple Level Cell) stores 3 bits - hence 8 levels - so the voltage difference between levels is half as much, and so is the margin between levels.
Everything deep down is analog, so the digital circuitry actually stores analog values on the cells at then reads them back and converts them to digital. When reading that analog value, the digital circuit has to decide to which digital value that analog value actual maps to, which it does by basically accepting any analog value within a certain range aroun the mathematically perfect value for that digital state.
(A simple example: in a 3.3V data line, when the I/O pin of a microcontroller reads the voltage it will decide for example that anything below 1.2V is a digital LOW (i.e. a zero), anything above 2.1V is a HIGH (a one) and anything in between is an erroneous value - i.e. no signal or a corrupted signal - this by the way is why if you make the line between a sender and a receiver digital chip too long, many meters, or change the signals in them too fast, hundreds of MHz+, without any special techniques to preserve signal integrity, the receiver will mainly read garbage)
So the more digital levels in a single cell the narrower the margin, the more likely that due to the natural decay over time of the stored signal or due cell damage from repeat writes, the analog value the digital circuitry reads from it be too far away from the stored digital level and be at best marked as erroneous or at worse be at a different level and thus yield a different digital value.
All this to say that QLC has less endurance (i.e. after fewer writes the damage to the cells from use causes that what is read is not the same value as what was written) and it also has less retention (i.e. if the cell is not powered, the signal decay will more quickly cause stored values to end up at a different level than when written).
Now, whilst for powered systems the retention problem is not much of an issue for cloud storage (when powered, the system automatically goes through each cell, reading its value and writting it back to refresh what’s stored there back to the mathematically perfect analog value) with just a slightly higher consumption over time for data that’s mainly read only (for flash memory, writting uses way more power than reading), the endurance problem is much worse for QLC because the cells will age twice as fast over TLC for data that is frequently written (wear-leveling exists to spreads this effect over all cells thus giving higher overall endurance, but wear-leveling is also in there for TLC so it does not improve the endurance of QLC).